1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus and, more particularly, to a circuit for outputting data in a semiconductor memory apparatus.
2. Related Art
As shown in FIG. 1, a conventional data output circuit of a semiconductor memory apparatus includes a clock synchronization unit 10 and a data output driver 20.
The clock synchronization unit 10 receives data and outputs first synchronization data “data_clk1” and second synchronization “data data_clk2” in synchronization with rising and falling clocks “Rclk” and “Fclk”. The data output driver 20 generates output data “DQ” by driving the first synchronization data “data_clk1” and the second synchronization data “data_clk2.”
At this time, the clock synchronization unit 10 is configured to receive a power supply voltage (VDD) as a driving voltage thereof. The data output driver 20 is configured to receive a power supply voltage for inputting/outputting data (VDDQ) (hereinafter, I/O power supply voltage) as a driving voltage thereof. Although the power supply voltage (VDD) and the I/O power supply voltage (VDDQ) have the same target voltage level, the power source of the power supply voltage (VDD) is different from that of the I/O power supply voltage (VDDQ). Although the two voltages have the same target voltage level from different power sources, they have different characteristics of noises according to the number of operating circuits. Thus, if the level difference between the two voltages occurs due to their different noise characteristics, there occurs a problem in that bits of the output data “DQ” are overlapped.
Referring to FIG. 2, in case of the first synchronization data “data_clk1” if the power supply voltage (VDD) becomes higher than the I/O power supply voltage (VDDQ), the phase of the first synchronization “data data_clk1” lags behind that of the output data “DQ”. Meanwhile, if the power supply voltage (VDD) becomes lower than the I/O power supply voltage (VDDQ), the phase of the output data “DQ” lags behind that of the first synchronization data “data_clk1.”
Since the data output driver 20 outputs the output data “DQ” to the same node in response to the first synchronization data “data_clk1” and the second synchronization data “data_clk2,” there can be caused a problem in that the bits of the output data “DQ” can be overlapped.